The fabrication of non-volatile memory (NVM) devices may be integrated into a complementary metal oxide semiconductor (CMOS) foundry process flow. The current state of the art integrates the more complicated floating gate NVM foundry process into foundry process flow for technologies such as field-programmable gate arrays (FPGAs). Recent interest and trends redirect interest towards silicon oxide nitride oxide silicon (SONOS) NVM because of its limited additional process burden and the ability to program (and erase) SONOS NVM at lower voltages.
Examples of embedding SONOS NVM into a CMOS foundry process flow are described in, for example, U.S. Pat. No. 6,946,349, entitled “Method for Integrating a SONOS Gate Oxide Transistor into a Logic/Analog Integrated Circuit Having Several Gate Oxide Thicknesses” (the '349 patent) and U.S. Pat. No. 7,361,560, entitled “Method of Manufacturing a Dielectric Layer in a Memory Device that Includes Nitriding Step” (the '560 patent). However, these patents merely describe the basic concept of embedding SONOS without showing how SONOS NVMs are embedded into a standard CMOS foundry process with the least amount of processing overhead or burden on the standard CMOS foundry process. None of the methods described in these patents or elsewhere teach how to minimize process overhead or burden on standard CMOS foundry process.